High-density, high-speed, non-volatile, low-power, and low-cost are common goals shared by many memory devices. But all these cannot be realistically obtained in practice, and some trade-offs are inevitable. The particular applications dictate which way the compromises should be made. For example, static random access memory (SRAM) is fast, but usually comes at the cost of lower density. Such is useful in CPU-cache memory applications. Dynamic random access memory (DRAM) is high density, but is not non-volatile. So DRAM is usually used in main memory applications for general purpose computers.
Newer memory types like magnetic random access memory (MRAM) are inherently non-volatile, but still have to find compromises between density, access speed, etc. Three types of MRAM have been developed based on different magnetic phenomenon, e.g., anisotropic, giant, and tunneling magneto resistance.
The tunneling magneto resistance type of MRAM is of interest here. A cross-point array of magnetic tunneling junction (MJT) memory cells allows direct addressing. Each cell appears as a resistance that depends on the digital data value being stored.
The conventional MJT memory cell comprises two magnetic layers separated by an electrical insulator. The insulator is so thin that it is subject to tunneling currents between the magnetic layers it contacts. Such tunnel currents appear as an electrical resistance that depends on the magnetic field that cuts through the insulator. The upper and lower magnetic layers are deposited as ellipsoids so that their magnetizations will occur in one of two preferred directions, e.g., longitudinal with the ellipsoid.
The lower magnetic layer is fabricated with a high coercitivity material and is permanently magnetized in a set direction during an annealing process step. The upper magnetic layer comprises a lower coercitivity material and is flip-flopped in its magnetic direction by column and row data-write currents that agree at the targeted cross-point array intersection.
The magnetic field experienced by the insulator sandwiched in between the upper and lower magnetic layers will be in one of two states, a first where both magnetic directions are the same, and a second where the magnetic directions are opposite. The magnetic field affects the ease with which tunneling electrons with spin can punch or tunnel through the insulator. So the state of the upper magnetic “data” layer can be read by measuring the apparent electric resistance across the insulator.
Hewlett-Packard MRAM technology includes cross-point arrays of MJT cells in which differential measurements of each MJT cell's electrical resistance are measured. If the reading causes the upper magnetic layer magnetic direction to flip, a current is generated that can be sensed. Such then allows a data-write cycle to be generated that restores the bits disturbed during an “equipotential” read cycle.
Building large arrays of memory cells has been a problem because the data-write currents seen by particular cells can be reduced by spurious leakage paths through non-selected cells. The bit lines and word lines connect to rows and columns of memory cells, and it is the memory cell at the intersection of the selected bit line and selected word line that is intended to receive all the data-write current. But other memory cells laying on a selected bit line, or on a selected word line can participate in a leakage path that serpentines through multiple memory cells in series. Each memory cell appears as a programmable resistance, and these can load the individual bit lines and word lines. The practical effect is such bit and word lines are limited in length and thus the size of the array is also limited. Another effect is the operating margins are reduced.
What is needed is a circuit to limit or control such leakage currents so the bit and word lines are not so loaded and larger arrays can be fabricated.